1. Field of the Invention
The present invention relates to phase locked loop systems and, in particular, to a pulse density modulation technique for translating a multi-bit phase error input into a high resolution control signal for a stepped multi-phase clock generator.
2. Discussion of the Prior Art
A phase locked loop (PLL) is a frequency-selective feedback system which synchronizes with an input signal and then tracks changes in input signal frequency.
As shown in the FIG. 1, a basic analog PLL 10 includes three primary elements: a phase detector, a loop filter with some gain, and a voltage controlled oscillator (VCO).
The frequency of the input signal to the PLL 10 has an instantaneous phase .phi..sub.i (s). The instantaneous phase of the VCO output frequency is .phi..sub.o (s). The input and output phases are compared by the phase detector to provide a phase error .phi..sub.e (s).
The phase error .phi..sub.e (s) can be expressed in Laplace notation as ##EQU1## where K.sub.d (volts per radian) is the gain constant of the phase detector.
The output voltage of the phase detector is filtered by the loop filter utilizing a loop transfer function F(s) which rejects out-of-band noise and high-frequency signal components. The output voltage of the loop filter is given by ##EQU2##
The corresponding change in the output frequency of the VCO is EQU .DELTA.W=K.sub.2 V.sub.2 (s)
where K.sub.2 (radians per second per volt) is the gain constant of the VCO.
Since ##EQU3##
Combining the above equations provides the basic loop transfer function ##EQU4## where K=K.sub.2 K.sub.d. Also, as stated above EQU .phi..sub.e (s)=.phi..sub.i (s)-.phi..sub.o (s)
Therefore, ##EQU5##
The PLL 10 behaves like any feedback system. For proper operation of the loop 10, three parameters must be chosen independently, depending upon the application: (1) the natural frequency W.sub.n of the loop, (2) a damping factor .zeta., and (3) the DC loop gain K.sub.v =KF(o), where F(o) is the DC gain of the loop filter 14.
For a basic first-order PLL, the loop filter is omitted. Thus, F(S)=1 and the basic loop transfer function becomes ##EQU6##
Since the only variable in a first-order loop is K.sub.v =K, the usefulness of a first-order loop is very limited.
In many applications, it is desirable to utilize a second-order loop filter configured as shown in FIG. 2, which illustrates an active filter using an operational amplifier. For this configuration, the loop transfer function becomes ##EQU7##
The active filter transfer function is given by ##EQU8##
This is referred to as a proportional-plus-integral control, since the transfer function F(s) comprises the sum of a term which is proportional to the phase error and a term which represents the integration or accumulation of the phase error over time.
As shown in FIG. 3, the transfer function F(s) may be realized by two active filters operating in parallel, one for the proportional term R.sub.2 /R.sub.1 and one for the integral term 1/SCR.sub.1. The proportional and integral terms are then added to provide the control signal for the VCO 16.
Both of these latter configurations permit independent choice of W.sub.n, .zeta., and K.sub.v, and are widely used in practical PLL designs. The active filter has the added advantage that the presence of the amplifier makes the DC loop gain K.sub.v very high compared to that obtainable with the passive configuration. The active second-order loop filter is, therefore, the most attractive choice for most applications.
A digital PLL (DPLL) is a discrete time version of the above-described analog PLL. In a DPLL, the phase error is sampled and quantized in an analog-to-digital (A/D) converter and then processed in a digital discrete time filter. The discrete output of the filter is converted into analog samples by a digital/analog converter and then held in a zero-order hold circuit the output of which controls the VCO.
A simpler type of digital PLL, sometimes referred to as a digital phase synchronizer, can be used to provide a stepping signal for advancing or retarding a multi-phase clock generator or digitally controlled clock. In this type of PLL, the sign of the discrete phase error value generated by the A/D converter determines whether the control output of the PLL will advance or retard the stepped clock generator. That is, if during a cycle of the sample clock generated by the clock generator, the input phase advances relative to the phase of the sample clock, then an advance signal is provided to the clock generator to cause a forward phase jump. Conversely, if the input phase lags relative to the phase of the sample clock output of the clock generator, then a retard signal is provided to cause a backward phase jump.
A major problem associated with this so-called "bang-bang" approach to phase clock control is that the single-bit sign value utilized to drive the advance/retard signal can only implement single-phase movement of the clock generator in a given cycle of the sample clock and, therefore, does not provide the fine resolution required in high speed data recovery applications.